| 摘要 |
It is a verification device of semiconductor integrated circuit configured to verify the equivalence of circuit description and assertion description. The device includes an assertion based verification unit configured to perform assertion based verification of the circuit description on the basis of the assertion description, and generating pass information when the operation of the signal described in the assertion description conforming to a preliminary condition is observed in the circuit description, or generating failure information when the operation of the signal is not observed in the circuit description, a logic generating unit configured to extract a signal corresponding to the failure information from the assertion description, and generating an input/output logic of the circuit description from the extracted signal, a signal restriction generating unit configured to generate a signal restriction on the basis of the input/output logic generated by the logic generating unit, and an estimating unit configured to evaluate the validity of the signal restriction generated by the signal restriction generating unit.
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