发明名称 OFFSET CANCELLATION CIRCUIT AND DISPLAY DEVICE
摘要 In an offset cancellation circuit according to the present invention, a first capacitance is connected to a gate of a first transistor of a first active load, and a second capacitance is connected to a gate of a second transistor of the first active load. A switch sets a first time period and a second time period in connection states between the first and second transistors and the first and second capacitances. The connection states between the first and second transistors and the first and second capacitances are set so that a gate voltage of the first transistor is supplied to the first capacitance, and a gate voltage of the second transistor is supplied to the second capacitance during the first time period; and so that the first and second capacitances can retain charges, and the second time period becomes an output time period of the operational amplifier during the second time period.
申请公布号 US2009289703(A1) 申请公布日期 2009.11.26
申请号 US20090435880 申请日期 2009.05.05
申请人 KOJIMA TOMOKAZU;MIZUKI MAKOTO 发明人 KOJIMA TOMOKAZU;MIZUKI MAKOTO
分类号 H03F1/02;H03L5/00 主分类号 H03F1/02
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