发明名称 COMBINATIONAL LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To avoid unnecessary power consumption by actively removing hazard occurrence even when an input signal to a combinational logic circuit composed of a multi-stage logic gate such a Galois field inverse element calculating circuit has an excessive transition. SOLUTION: In the combinational logic circuit constituted by further connecting two or more stages of logic circuits in which two or more stages of logic gate circuits are connected to perform predetermined arithmetic processing, an initial-stage logic gate circuit of one or more logic circuits including a final-stage logic circuit among the logic circuits performs mode switching between an operation mode wherein a last arithmetic result is held until a value of an input signal is determined and the held value is output and an operation mode wherein an arithmetic result associated with the input signal is output after the value of the input signal is determined based upon a control signal. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2009272804(A) 申请公布日期 2009.11.19
申请号 JP20080120374 申请日期 2008.05.02
申请人 NIPPON TELEGR & TELEPH CORP <NTT>;NTT ELECTORNICS CORP 发明人 YAMAKOSHI KOYO;YAMAGISHI AKIHIRO;HARADA MITSURU;OKAMOTO AKIO
分类号 H03K19/096 主分类号 H03K19/096
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