| 摘要 |
<P>PROBLEM TO BE SOLVED: To appropriately transmit/receive data even if the cycle of a clock signal of a client is changed with respect to a clock signal of a host. Ž<P>SOLUTION: A host circuit 4 is configured to hold a potential of a bus 7 at Low potential for 1 GBT and to then send bit values of address data to the bus 7 sequentially for the unit of 1 GBT. Furthermore, each of a plurality of client circuits 6<SB>1</SB>-6<SB>m</SB>measures the time during which the bus 7 is held at the Low potential and synchronously to the measured time, bit values of address data sent to the bus 7 are sequentially detected. Thus, even if a term of a clock signal of the client circuit 6<SB>1</SB>-6<SB>m</SB>is changed with respect to a clock signal of a host circuit 4, for example, it may be possible to appropriately transmit/receive address data between the host circuit 4 and the plurality of client circuits 6<SB>1</SB>-6<SB>m</SB>. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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