| 摘要 |
<P>PROBLEM TO BE SOLVED: To eliminate a deadlock due to waiting until data are held in a buffer in data processing for stream data or the like. Ž<P>SOLUTION: A FIFO (First-In First-Out) buffer 110 holds the stream data to a stream processing coprocessor from a DMA (Direct Memory Access) control part. A timer circuit 130 counts the time during which a transfer request is continuously output to the DMA control part. When a time-out in the timer circuit 130 is detected by a time-out detection circuit 140, the contents held in a dummy data register 161 is supplied to the FIFO buffer 110. Immediately after DMA transfer is completed (DMA_END=1), dummy data are inserted. During the DMA transfer (DMA_BSY=1), regardless of a time-out signal TMOUT, the insertion of the dummy data is prohibited. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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