发明名称 |
Asynchronous phase acquisition unit with dithering |
摘要 |
A digital phase locked loop includes a phase acquisition unit receiving a sampled input signal and applying its output to a first input of a digital phase detector, a digital controlled oscillator producing a digital output, and a feedback path coupling the digital output of the digital controlled oscillator to a second input of the digital phase detector in the digital domain. The input signal may be sampled asynchronously.
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申请公布号 |
US7619483(B2) |
申请公布日期 |
2009.11.17 |
申请号 |
US20070939948 |
申请日期 |
2007.11.14 |
申请人 |
ZARLINK SEMICONDUCTOR INC. |
发明人 |
VAN DER VALK ROBERTUS LAURENTIUS;SCHRAM PAULUS HENDRICUS LODEWIJK MARIA;SITCH DOUGLAS ROBERT |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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