| 摘要 |
PROBLEM TO BE SOLVED: To suppress an increase in layout area and to reduce an imbalance of the horizontal and vertical aspect of a bit cell of a dual port SRAM. SOLUTION: Transmission transistors FA1, FA2 for an A port are adjacently arranged each other to one end of the bit cell, concurrently, transmission transistors FB1, FB2 for a B port are adjacently arranged each other to the other end of the bit cell. Bit lines BLAc, BLAt for the A port are adjacently arranged each other by sharing the gate electrodes of the transmission transistors FA1, FA2 for the A port, and bit lines BLBc, BLBt for the B port are adjacently arranged each other by sharing the gate electrodes of the transmission transistors FB1, FB2 for the B port. COPYRIGHT: (C)2010,JPO&INPIT
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