发明名称 FOUR-TERMINAL MULTIPLE-TIME PROGRAMMABLE MEMORY BITCELL AND ARRAY ARCHITECTURE
摘要 <p>Embodiments disclosed herein relate to a non-volatile memory bitcell (1) and arrays thereof, methods of detecting whether the bitcell is in a programmed state, methods of detecting whether the bitcell is in an erased state, methods of setting the bitcell in a programmed state and methods of setting the bitcell in an erased state. The non- volatile memory bitcell may be a four terminal bitcell. The bitcell may have a pull-up electrode (2), a pull-down electrode (4), a cantilever electrode (5) and a contact electrode (3). An NMOS transistor may be coupled to the contact electrode. Depending upon the orientation of the word line, the current through the bitcell may be measured on the bitline, the data line or the pull-down electrode.</p>
申请公布号 WO2009135017(A1) 申请公布日期 2009.11.05
申请号 WO2009US42336 申请日期 2009.04.30
申请人 CAVENDISH KINETICS INC.;VAN KAMPEN, ROBERTUS, PETRUS 发明人 VAN KAMPEN, ROBERTUS, PETRUS
分类号 G11C23/00;H01H59/00 主分类号 G11C23/00
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