发明名称 |
DUAL PHASE DETECTOR PHASE-LOCKED LOOP |
摘要 |
A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duration that compensates for a phase error in the feedback signal. |
申请公布号 |
WO2009109640(A3) |
申请公布日期 |
2009.11.05 |
申请号 |
WO2009EP52634 |
申请日期 |
2009.03.05 |
申请人 |
CAMBRIDGE SILICON RADIO;LAMANNA, PASQUALE;SORNIN, NICOLAS |
发明人 |
LAMANNA, PASQUALE;SORNIN, NICOLAS |
分类号 |
H03L7/087;H03L7/089;H03L7/095;H03L7/191;H03L7/197 |
主分类号 |
H03L7/087 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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