发明名称
摘要 In an LDMOS, a p<+>-type anode layer (21) is formed adjacent to an n<+>-type drain layer (16). The anode layer (21) makes no contribution to an operation of the LDMOS at a rated voltage and generates holes at the time of ESD. The holes flow into the base layer (14) through the active layer (13). Electrons flow from a source layer (15) into the drain layer (16) through the active layer (13). A parasitic thyristor of the LDMOS thus operates, with the result that a source-to-drain holding voltage can be lowered when a large current flows and the current distribution can be uniformed. <IMAGE>
申请公布号 JP4357127(B2) 申请公布日期 2009.11.04
申请号 JP20010050776 申请日期 2001.02.26
申请人 发明人
分类号 H01L27/04;H01L29/78;H01L21/336;H01L21/822;H01L27/06;H01L29/739;H01L29/749;H01L29/786 主分类号 H01L27/04
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