发明名称 Processing multiplex sublayer data unit data in hardware
摘要 The present invention concerns an apparatus comprising a data unit, a memory and a control unit. The data unit may be configured to generate an output signal comprising a series of frames each having a header and a payload in response to an input signal comprising a series of words. The memory may be configured to hold the output signal and to interface with a device. The control unit may be configured to present one or more control signals configured to control the data unit and the memory.
申请公布号 US7613186(B2) 申请公布日期 2009.11.03
申请号 US20040840492 申请日期 2004.05.06
申请人 VIA TELECOM CO., LTD. 发明人 SAADO ALON
分类号 H04L12/28;H04L12/56;H04L29/02 主分类号 H04L12/28
代理机构 代理人
主权项
地址