| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of enhancing the process margin of the semiconductor device. <P>SOLUTION: The semiconductor memory includes two bit lines BL1, BL2 provided in the same wiring layer; an active region AA2 provided in a memory cell array; two word lines WL1, WL2 intersecting with the active region AA2; first and second transistors Tr1, Tr2 provided on the active region AA2 and having gates connected to the word lines WL1, WL2 respectively; a first resistive storage element MTJ1 connected to the bit line BL2 and a source/drain of the transistor Tr1; a second resistive storage element MTJ2 connected to the bit line BL2 and a source/drain of the transistor Tr2; and a wiring layer M2 connected to the bit line BL1 and a common node of two transistors Tr1, Tr2 and disposed between the word line WL1 and WL2. The active region AA2 extends from one edge of the memory cell array to the other edge thereof. <P>COPYRIGHT: (C)2010,JPO&INPIT |
