发明名称 VARIABLE DELAY CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To continuously set fine delay time highly accurately in a wide variable width without being limited to the variable range of a variable load capacity in a simple and small-sized configuration. Ž<P>SOLUTION: A variable delay circuit comprises: a delay part A and a delay part B connected in parallel between an input terminal and an output terminal, for outputting the input signals of the input terminal to the output terminal with delay time Ta and Tb (Ta>Tb) when operated alone respectively; and a current control part for inputting analog control signals X and Y, changing a current amount flowing to the delay part A and the delay part B correspondingly to the difference (X-Y), and setting the delay time continuously changing correspondingly to the difference (X-Y) between the delay time Ta and Tb. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2009253366(A) 申请公布日期 2009.10.29
申请号 JP20080095186 申请日期 2008.04.01
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KATSURAI HIROAKI;TERADA JUN
分类号 H03K5/14 主分类号 H03K5/14
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