发明名称 Plating buss and a method of use thereof
摘要 The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly, the invention encompasses a serpentine plating buss which increases the PCB singulation process window thereby minimizing short circuit problems due to indexing errors caused by occasional manufacturing and equipment alignment problems. The serpentine plating buss design therefore increases board yield.
申请公布号 US7608788(B2) 申请公布日期 2009.10.27
申请号 US20070869204 申请日期 2007.10.09
申请人 发明人 JOHNSON MARK S.
分类号 H01R12/04;H05K1/11 主分类号 H01R12/04
代理机构 代理人
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