| 摘要 |
<p>The method includes predetermining an output enable time period by measuring the maximum settling time when a signal is read during a transition from 0 to 1 or vice versa, and multiplying the maximum settling time by a safety factor 2.5, to set an output enable time period; reading and latching an input value; and transmitting the latched value onward after the predetermined output enable time period. An embodiment of the apparatus 10 includes two inverters 12, 14 and two pass gates 16, 18 and connected to a line 20 at its input. The pass gates 16, 18 are connected in a multiplexer configuration. A third pass gate 30 for connecting line 32, carrying the (inverted) output B of the metalatch, to further circuit portions, according to a 2-bit output enable signal applied to control lines 34, 36 respectively. In alternate embodiments, other logic circuit portions already provided can perform the function of pass gate 30.</p> |
