发明名称 |
BRANCH PREDICTION USING A BRANCH TARGET ADDRESS CACHE IN A PROCESSOR WITH A VARIABLE LENGTH INSTRUCTION SET |
摘要 |
In a variable-length instruction set wherein the length of each instruction is a multiple of a minimum instruction length granularity, an indication of the last granularity (i.e., the end) of a taken branch instruction is a stored in a branch target address cache (BTAC). If a branch instruction that later hits in the BTAC is predicted taken, previously fetched instructions are flushed from the pipeline beginning immediately past the indicated end of the branch instruction. This technique saves BTAC space by avoiding to the need to store the length of the branch instruction in the BTAC, and improves performance by eliminating the necessity of calculating where to begin flushing (based on the length of the branch instruction). |
申请公布号 |
WO2008021828(A3) |
申请公布日期 |
2009.10.22 |
申请号 |
WO2007US75363 |
申请日期 |
2007.08.07 |
申请人 |
QUALCOMM INCORPORATED;STEMPEL, BRIAN MICHAEL;SMITH, RODNEY WAYNE |
发明人 |
STEMPEL, BRIAN MICHAEL;SMITH, RODNEY WAYNE |
分类号 |
G06F9/30;G06F9/38 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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