发明名称 Wafer level semiconductor package and method for manufacturing the same
摘要 <p>A wafer level semiconductor package is provided to improve the reliability for the solder joint of motherboard and solder ball. The wafer(10) level semiconductor package is comprised of a wafer, a polymer, a via hole(24), a filler(26) and a solder ball(20). The polymer is coated on the wafer upper side including the bond pad(12). The polymer has the coefficient of thermal expansion which is similar to that of the motherboard. The via hole is penetrated so that the electricity can be flowed to the bonding pad from the backside surface of wafer. The conductive filler is filled in the via hole. The solder ball is melted to connect with the conductive filler for electricity in the entrance of the via hole.</p>
申请公布号 KR100922309(B1) 申请公布日期 2009.10.21
申请号 KR20070129176 申请日期 2007.12.12
申请人 发明人
分类号 H01L23/488 主分类号 H01L23/488
代理机构 代理人
主权项
地址