| 摘要 |
PURPOSE: A register controlled delay locked loop circuit is provided to prevent a jitter having the big value in the clock through the delay locking operation. CONSTITUTION: The register controlled delay locked loop circuit includes the phase comparison and the clock delay and the delay replication model. The phase comparison compares the phase of the source clock and feedback clock. The clock delay delays the phase of the internal clock corresponded to the clock edge of the source clock in response to the output signal of the phase comparison means. The clock delay delays the delay amount to the predetermined delay amount by first delay unit. The delay replication model outputs as the feedback clock by reflecting the real delay condition of the source clock. |
