| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus that reduces the number of unusable tester pins even when a pin multiplex function is used, and also reduces the number of processes for creating data necessary for generation of a test signal. Ž<P>SOLUTION: A formatter 1 provided in a semiconductor testing apparatus includes: waveform shaping circuits 11a and 11b that output signals S11 and S21 which defines rising and falling edges of a test signal; OR circuits 12a and 12b capable of aggregating the signals S11 and S21; edge converting circuits 14a and 14b for counterchanging rising and falling edges defined by signals S12 and S22 outputted from the OR circuits 12a and 12b; and flip-flop circuits 15a and 15b that generate output signals S1 and S2 with use of signals outputted from the edge converting circuits 14a and 14b. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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