| 摘要 |
An embodiment of the present invention is a technique to assemble multi-core dice. A first socket has first N sets of front side bus (FSB) contacts to house a first package having first 2N dice. Each of the first 2N dice has M cores. N and M are positive integers. A first chipset has 2N FSB signal groups interfacing to the first package via the first N sets of FSB contacts using first N FSB signal groups of the 2N FSB signal groups.
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