| 摘要 |
An on-die termination method to support a multi-chip package routing topology is described. The on die termination method may increase the surface area on the substrate such that larger size die or more memory may be mounted thereto. The on-die termination method may include a semiconductor package that features on die termination bumps coupled to a semiconductor die's bus terminals, which couples the semiconductor die to an on-die termination pin coupled in the motherboard. An alternative on-die termination method includes a semiconductor die, within the multi-chip CPU package, designated as an end agent from which a single on die termination bump is coupled to an on-die termination pin. |
