发明名称 Method and system for conducting design explorations of an integrated circuit
摘要 Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.
申请公布号 US7603643(B2) 申请公布日期 2009.10.13
申请号 US20070700284 申请日期 2007.01.30
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 MCCRACKEN THADDEUS CLAY;LEE JONG-CHANG;WU PING-CHIH;NGHIEM CECILE;CHEONG KIT LAM;EICHENSEER PATRICK JOHN
分类号 G06F17/50 主分类号 G06F17/50
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