| 摘要 |
<P>PROBLEM TO BE SOLVED: To avoid a resistance delay in a selective gate region and a peripheral circuit region while miniaturizing a memory cell array region, and to form simultaneously gates in the memory cell array region, the selective gate region and the peripheral circuit region. Ž<P>SOLUTION: The semiconductor device comprises: a semiconductor layer; first insulating films 12 formed in the memory cell array region and the selective gate region on the semiconductor layer; first electrode layers 13 formed on the first insulating layer 12; a plurality of element isolating regions 15 comprising element isolating insulating films formed to extend through the first electrode layer 13 and the first insulating film 12 to reach the inside of the semiconductor layer and self-aligned with the first electrode layers 13 to isolate an element region 10; a second insulating film 16 formed on the first electrode layer 13 over the element isolating regions 15, and having a first opening 17 exposing a surface of the first electrode layer 13 in the selective gate region; and second electrode layers 18 formed on the second insulating film 16 and on the exposed surface of the first electrode layer 13, and electrically connected to the first electrode layer 13 via the first opening 17. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
|
