CLOCK SIGNAL GENERATING ARRANGEMENT FOR A COMMUNICATION DEVICE

摘要

A clock signal generating arrangement (15) for a communication device (2) generates a system clock signal at an output (19) for use as a timing reference. The clock signal generating arrangement (15) comprises a reference clock generator (20) for generating a reference clock signal, a main clock generator (18) for generating a main clock signal having a greater accuracy than the reference clock signal, a clock adjust circuit (18) coupled to the reference clock generator for generating a compensated reference clock signal to compensate for error in the reference clock signal and a clock signal selector (34) coupled to the reference clock generator (20), the main clock generator (18) and the clock adjust circuit (18). The clock signal selector (34) selectively provides to the output (19) of the clock signal generating arrangement (15) as the system clock signal the compensated reference clock signal when an error in the reference clock signal reaches a first predetermined threshold (40) and until the error in the reference clock signal has been compensated and otherwise the reference clock signal when the communication device (2) is operating in an idle mode or the main clock signal when the communication device is operating in an active mode.