| 摘要 |
The storage system includes a first memory device configured to store data sent from a host system, a first memory device controller configured to control read/write access of the data from/to the first memory device, an arithmetic circuit unit configured to calculate parity data based on the data, a second memory device configured to store the parity data, a second memory device controller configured to control read/write access of the parity data from/to the second memory device. With this storage system, read access speed of the first memory device is faster than read access speed of the second memory device.
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