ADDER FOR GF(3), MULTIPLIER FOR GF(3), APPARATUS FOR COMPUTING UNIFIED ADDITION SUBTRACTION FOR GF(3) AND APPARATUS FOR MSB FIRST GF(3^M) SERIAL MULTIPLICATION

摘要

PURPOSE: A GF(3)-based adder, a GF(3)-based multiplier, a GF(3)-based addition/subtraction-integrated computing device and an MSBfirstGF(3^m) serial multiplier are provided to reduce the time delay and space complexity by performing the addition, subtraction and multiplication through the smaller number of gates for the GF(3) operation. CONSTITUTION: A GF(3)-based adder(740) comprises the first XOR gate, the second XOR gate, an AND gate, the third XOR gate, the fourth XOR gate, and an OR gate. The first XOR gate performs the exclusive OR operation by using ai^H, the code bit of an ai, and bi^L, the data bit of a bi as input values. The second XOR gate performs the exclusive OR operation by using ai^H, the data bit of an ai, and bi^L, the code bit of the bi as input values. The AND gate generates ri^H, the code bit of an ri.