| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a signal recovery circuit capable of enlarging reception margin. <P>SOLUTION: A signal reproducing circuit comprises: a clock signal generating section CLK_GEN for generating a clock signal CLKa, CLKb, CLKc; a clock/data decision section CD_JGE for generating a phase detection signal (EARLY, LATE), when the edge of a data signal Di enters an interval between CLKa and CLKb or between CLKb and CLKc; a window width control section WW_CTL, and the like. The CLK_GEN controls entire phases of CLKa, CLKb, CLKc, while maintaining the phase differences from one another so that the edge of the Di does not enter the gap, on the basis of the phase detecting signal, and controls the phase difference between CLKa and CLKb and the phase difference between CLKb and CLKc, on the basis of a signal (Sww) from the WW_CTL. <P>COPYRIGHT: (C)2009,JPO&INPIT |
