| 摘要 |
An output clock recovery circuit (10) for recovering an output clock (14) from a source clock (12) and time stamp information (18A, 18B) includes a time stamp translator (22) and a phase-locked loop circuit (17) including a fraction processor (34). The time stamp translator (22) receives the time stamp information (18A, 18B). The time stamp translator (22) uses an algorithm that translates the time stamp information (18A, 18B) into a time stamp decimal component (48) and a time stamp integer component (50). The time stamp decimal component (48) is less than one and is processed by the fraction processor (34). The time stamp integer component (50) is maintained within a predetermined range of integers that are greater than zero. The predetermined range can vary. The time stamp translator (22) determines a value R, which equals the ratio of the output clock frequency to the source clock frequency times a constant. The algorithm can include a multiplier P that varies depending upon the value of R. The time stamp decimal component (48) and the time stamp integer component (50) can be derived by multiplying P times R/10. The output of the fraction processor (34) and the time stamp integer component (50) can be input into a feedback divider (36) of a feedback loop of the phase-locked loop circuit (17) to recover the output clock (14). The fraction processor (34) can include a fraction accumulator or a delta-sigma type of fractional-N phase-locked loop circuit.
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