| 摘要 |
<P>PROBLEM TO BE SOLVED: To maintain stable oscillation for a long period, even when abnormality is generated in a reference standard signal. <P>SOLUTION: A phase-locked loop (PLL) oscillation circuit is provided with an average value calculation part 14 for calculating the average value AVE of a control voltage VC1, in a normal operation state and a transient data storing/output part 15 for storing a state of the control voltage VC1 in the latest prescribed time, wherein when step-out is generated due to abnormality of a reference standard signal REF; a control voltage VC2 for performing phase correction is generated based on transient data TRA, immediately prior to step-out which is stored in the transient data storing/output part 15, and then the control voltage VC2 is generated, based on the average value AVE calculated by the average value calculation part 14 and applied to a VCO 20. Consequently, a phase shift generated from the step-out detection up to a free-run state is corrected, and further, during a period that the reference standard signal REF is restored to a normal state, free runs can be continued by the suitable control voltage VC2. <P>COPYRIGHT: (C)2009,JPO&INPIT |
