发明名称 Method and apparatus for soft-error immune and self-correcting latches
摘要 A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system.
申请公布号 US7590907(B2) 申请公布日期 2009.09.15
申请号 US20080168147 申请日期 2008.07.06
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 DRAKE ALAN J.;KLEINOSOWSKI AJ;MARTIN ANDREW K.
分类号 G01R31/28 主分类号 G01R31/28
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