发明名称 Test structure for electrically verifying the depths of trench-etching in an SOI wafer, and associated working methods
摘要 The invention provides a simple to implement and reliable recognition of the moment at which insulation trenches reach the buried insulating layer during an etch process. The technological reliability during the etching of such trenches is increased, the production of refuse is prevented, and costs are reduced. To these ends, the invention provides a test structure for verifying an insulation trench etching in an SOI wafer. After an etching o insulation trenches, the test structure has a row of connected islands, whereby each island is surrounded by a trench. This trench has a different width form island to island (A,B; B,C) while including a trench width that appears the form of an insulation trench in an active circuit. A section of the surrounding trench (a,b) of each island (A,B) forms a common piece with the trench of adjacent islands. The respective section has, in the inner islands, the width of the adjacent trench having the next larger or the next smaller measure of width in the row.
申请公布号 US7588948(B2) 申请公布日期 2009.09.15
申请号 US20040552984 申请日期 2004.04.19
申请人 X-FAB SEMICONDUCTOR FOUNDRIES AG 发明人 LERNER RALF
分类号 H01L21/00;H01L23/544 主分类号 H01L21/00
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