发明名称 CONTROLLED EDGE THICKNESS IN SILICON WAFER
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a wafer in which the thickness of an epitaxial layer is controlled during processing so that a region close to the edge of the wafer has a thickness larger or smaller than the thickness of a region close to the center of the wafer, and to provide a method for manufacturing the wafer. <P>SOLUTION: The silicon wafer defines the center, the edge and the region close to the edge, and has a wafer epitaxial layer wherein the wafer has the first thickness of the epitaxial layer close to the center and the second thickness of the epitaxial layer of the region close to the edge, and in this case, the second thickness varies by at least about 2% compared to the first thickness. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009206516(A) 申请公布日期 2009.09.10
申请号 JP20090043692 申请日期 2009.02.26
申请人 SILTRONIC AG 发明人 LITE KEVIN;TRAN QUYNH
分类号 H01L21/205 主分类号 H01L21/205
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