发明名称 |
Interleaver memory selectably receiving PN or counter chain read address |
摘要 |
A method and apparatus for interleaving multiple frames of data as disclosed provide for an extremely streamlined approach to achieving both methods of interleaving as defined in the IS-2000 standard while meeting the complex requirement of frame puncturing. Output addressing is directly driven by a PN index or a counter locked to the reverse link timing, it is a simple manner of range selection to achieve all possible configurations required in the IS-2000 standard. Puncturing of sub-20 ms frames is also easily accomplished by using a single contiguous memory and interleaver engine that resides in the input side of the interleaver memory.
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申请公布号 |
US7586993(B2) |
申请公布日期 |
2009.09.08 |
申请号 |
US20010007087 |
申请日期 |
2001.12.06 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
RASTELLO PETER;MCDONOUGH JOHN G. |
分类号 |
H04L27/00;H04B1/707;H04L1/00 |
主分类号 |
H04L27/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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