发明名称 Programmable packet parsing processor
摘要 The present invention provides a packet processing device and method. A parsing processor provides instruction-driven content inspection of network packets at 10-Gbps and above with a parsing engine that executes parsing instructions. A flow state unit maintains statefulness of packet flows to allow content inspection across several related network packets. A state-graph unit traces state-graph nodes to keyword indications and/or parsing instructions. The parsing instructions can be derived from a high-level application to emulate user-friendly parsing logic. The parsing processor sends parsed packets to a network processor unit for further processing.
申请公布号 US7586851(B2) 申请公布日期 2009.09.08
申请号 US20040832796 申请日期 2004.04.26
申请人 CISCO TECHNOLOGY, INC. 发明人 PANIGRAHY RINA;LIU JACKIE;NG DANIEL YU-KWONG;JAIN SANJAY;BAGEPALLI NAGARAJ A.;PATRA ABHIJIT
分类号 H04L12/56;H04J1/16;H04L29/06 主分类号 H04L12/56
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