| 摘要 |
A data processing apparatus for summing data values includes: a plurality of adder logic stages arranged in parallel; a control logic, in response to a request to sum two data values, to forward portions of the two data values to respective ones of the plurality of adder logic stages, each of the plurality of adder logic stages performing a carry propagate addition of the received portions to generate an intermediate sum, a propagate value and a carry; and further logic stages for combining the intermediate sums, carries and propagate values to produce a sum of the two data values. The control logic, further in response to a request to add a third data value to the sum before the further logic has completed sum, forwards portions of the third data value to respective ones of the plurality of adder logic stages, feedbacks the intermediate sums, and selectively feedbacks a carry generated from a preceding adder logic stage. The plurality of adder logic stages perform a carry propagate addition of the fedback intermediate sums and carrys with respective portions of the third data value to generate a plurality of further intermediate sums, further carrys and further propagate values. The further logic stages combine the further intermediate sums, carries and propagate values to produce a sum of the three data values.
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