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发明名称
LAYOUT METHOD FOR VOLTAGE TRIMMING CIRCUIT IN SEMICONDUCTOR DEVICE
摘要
申请公布号
KR100913970(B1)
申请公布日期
2009.08.26
申请号
KR20080014579
申请日期
2008.02.18
申请人
发明人
分类号
G11C5/14;G11C8/08
主分类号
G11C5/14
代理机构
代理人
主权项
地址
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