A display device includes a display panel, a gate clock generator and a gate driver. The display panel includes a plurality of gate lines connected to a plurality of pixels. The gate clock generator generates a plurality of gate clock signals in which a width of a logic high period of a first gate clock signal is smaller than that of other gate clock signals during one frame period. The gate driver sequentially applies gate turn-on signals to the plurality of gate lines according to the gate clock signal and a gate clock bar signal having a phase opposite to the other gate clock signals.
