| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To manufacture a semiconductor integrated circuit accommodating a complicate clock selection circuit by a simple arrangement clustering process. <P>SOLUTION: This semiconductor integrated circuit is provided with: a clock tree circuit for delay-adjusting a clock signal by various delay amounts; and a clock synchronization circuit to which the delay-adjusted clock signal is supplied. The clock tree circuit is provided with: a first clock tree cell installed in the poststage of a clock signal introducing terminal; a second clock tree cell installed in the poststage of the first clock tree in the prestage of the clock synchronization circuit; and a clock ramification point installed in the prestage of the second clock tree cell. The clock synchronization circuit is provided with: a first clock synchronization circuit to which a clock signal delay-adjusted by the second clock tree cell is supplied; and a second clock synchronization circuit to which the clock signal to be output from the clock tree circuit is supplied at the clock ramification point. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
