| 摘要 |
The I/O circuit 1 is provided with a first NMOS driver 10 having a drain connected to a pad, a second NMOS driver 11 arranged in an active area which differs from the first NMOS driver 10 and having a drain connected to a source of the first NMOS driver 10 and a source connected to a ground potential, a level converter converting a level of an internal power source potential to a level of a power source potential, and a first NMOS transistor 26 having a drain connected to one output terminal of the level converter, a source connected to a ground potential, and a gate connected to another output of the level converter, and wherein the drain of the first NMOS transistor is connected to the gate of the second NMOS 11.
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