发明名称 |
EXPOSURE CONDITION SETTING METHOD, PATTERN DESIGNING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide a technology capable of improving the manufacture yield of a semiconductor integrated circuit. <P>SOLUTION: The exposure condition setting method includes: a step (ST1) of inputting design layout data; a step of extracting a plurality of gate patterns having a prescribed gate length from the inputted design layout data; a step (ST2) of calculating the dimension variation amount of a transfer pattern transferred and formed on a film to be transferred by exposing a mask pattern corresponding to the extracted gate patterns and the design value of the gate patterns; a step (ST3) of obtaining the distribution of the number of the gate patterns corresponding to the dimension variation amount of the gate patterns; and a step (ST4) of setting an exposure condition so that the dimension variation amount of the gate pattern indicating the mode or median of the gate pattern number distribution satisfies the condition of permission. <P>COPYRIGHT: (C)2009,JPO&INPIT |
申请公布号 |
JP2009182237(A) |
申请公布日期 |
2009.08.13 |
申请号 |
JP20080021405 |
申请日期 |
2008.01.31 |
申请人 |
TOSHIBA CORP |
发明人 |
USUI SATOSHI;TANAKA SATOSHI |
分类号 |
H01L21/027;G03F1/68;G03F1/70;G03F7/20 |
主分类号 |
H01L21/027 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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