发明名称 PHASE-LOCKED LOOP CIRCUIT AND DELAY-LOCKED LOOP CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a phase-locked loop circuit capable of preventing increase of jitter and fluctuation of a cut-off frequency, and to provide a delay-locked loop circuit. <P>SOLUTION: This phase-locked loop circuit includes: a phase comparator 101 that compares phases between a reference signal and a feedback signal and outputs a phase difference signal indicating a phase difference therebetween; a charge pump 102 that outputs a charge pump current according to the phase difference signal; a low-pass filter 103 that includes a resistor and a capacitor and that smoothes the charge pump current and converts the smoothed current into a control voltage; a voltage-controlled oscillator 104 that generates an oscillation signal with a frequency according to the control voltage; and a frequency divider 105 that generates a frequency-divided signal by frequency-dividing the oscillation signal and outputs the frequency-divided signal to the phase comparator as the feedback signal; and is characterized in that the resistor in the low-pass filter is a variable resistor changed according to the control voltage. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009182447(A) 申请公布日期 2009.08.13
申请号 JP20080018081 申请日期 2008.01.29
申请人 FUJITSU MICROELECTRONICS LTD 发明人 AZUMA HIROTO
分类号 H03L7/093 主分类号 H03L7/093
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