HIGH BANDWIDTH CACHE-TO-PROCESSING UNIT COMMUNICATION IN A MULTIPLE PROCESSOR/CACHE SYSTEM

摘要

A processor/cache assembly (72) has a processor die (10) coupled to a cache die (45). The processor die (10) has a plurality of processor units (11-35) arranged in an array. There is a plurality of processor sets of contact pads (103, 105) on the processor units, one processor set for each processor unit (11-35). Similarly, the cache die has a plurality of cache units (46-20) arranged in an array. There is a plurality of cache sets of contact pads (102, 104) on the cache die (45), one cache set for each cache unit (46-70). Each cache set (102, 104) is in contact with one corresponding processor set (103, 105).