| 摘要 |
<p>A digital filter (2) comprising delay elements (D0 - Dm-1), multipliers (MP0 - MPm), and an adder (ADD), receives a digitized FM or phase modulated signal as its input (Xin(t)), and generates an output signal (Y(t)). A unit (3) detects and smooths the envelope of the input signal (Xin(t)) to generate a direct-current reference signal (Vth(t)) as an evaluation criterion. An error detecting unit (4) calculates an error signal (e(t)) which is the difference between the reference signal (Vth(t)) and the desired signal (Y(t)). An error component limiting unit (5) determines and smooths the absolute value of the error signal (e(t)) to generate a direct-current error signal, and monitors whether the direct-current error signal exceeds a predetermined value or not. If the predetermined value is exceeded, the error component limiting unit (5) outputs a corrected error signal (ecp(t)) which is generated by suppressing the amplitude of the error signal (e(t)). The filter adjusts the tap weights (K0 - Km) of the multipliers (MP0 - MPm) so that the amplitudes of the error signal (e(t)) and the corrected error signal (ecp(t)) approach zero. This makes the entire system converge, thereby generating a signal (Y(t)) from which multipath distortion is eliminated.
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