发明名称 |
Solid-state image sensing device |
摘要 |
When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.
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申请公布号 |
US7573521(B2) |
申请公布日期 |
2009.08.11 |
申请号 |
US20060478685 |
申请日期 |
2006.07.03 |
申请人 |
SONY CORPORATION |
发明人 |
YOSHIHARA SATOSHI;MAKI YASUHITO |
分类号 |
H04N5/18;H04N5/217;H04N5/335;H04N5/341;H04N5/353;H04N5/361;H04N5/369;H04N5/372;H04N5/378 |
主分类号 |
H04N5/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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