发明名称 SAMPLE AND HOLD CIRCUIT, MULTIPLYING D/A CONVERTER AND A/D CONVERTER
摘要 PROBLEM TO BE SOLVED: To maintain an in-phase input voltage of an operational amplifier in a holding phase at a predetermined value and to enlarge an input voltage range. SOLUTION: In a sampling phase, at least one of Va to Vf serves as an input voltage Vin. In a holding phase, at least one of Vg to Vj serves as an input voltage Vin+ΔV, and at least a pair of an inverting-side capacitor and a non-inverting-side capacitor serves as a feedback capacitor. When total capacitance of the inverting-side capacitors to which the input voltage Vin is applied in the sampling phase is defined asαC, total capacitance of the non-inverting-side capacitors is defined asβC, total capacitance of the inverting-side capacitors to which the input voltage Vin+Δis applied in the holding phase is defined asγC and total capacitance of the non-inverting side capacitors is defined asηC,α+β=γ+η[first condition],γ=η[second condition],α≠β[third condition], and capacitance of the feedback capacitor=(α-β-γ+η)C×(N/2) [fourth condition] are established. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009177780(A) 申请公布日期 2009.08.06
申请号 JP20080216585 申请日期 2008.08.26
申请人 DENSO CORP 发明人 MAKIHARA TETSUYA;HORIE MASUMI
分类号 H03M1/12 主分类号 H03M1/12
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