发明名称 Decoding apparatus and integrated circuit
摘要 A first OS 200 is started, and start up of a second OS 300 is completed while a scramble key Ks is acquired and registered (step S201). The first OS 200 stores network settings information and program channel information (control information) in a state-storage buffer 103c (step S106), and the first OS 200 is shut down. The second OS 300 begins switch-to-SMP processing (step S204), and beings SMP processing (step S205). Thereafter, the control information is read from a state-storage buffer area 103a (step S206), and a first CPU 101a and a second CPU 101b share control of units of an AV decoder 101d (step S207).
申请公布号 EP1821539(A3) 申请公布日期 2009.08.05
申请号 EP20070250600 申请日期 2007.02.14
申请人 PANASONIC CORPORATION 发明人 WATANABE, T.;KITAMURA, A.
分类号 G06F9/445;H04L9/10;H04N7/167 主分类号 G06F9/445
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