发明名称 |
Transistors with stressed channels |
摘要 |
A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.
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申请公布号 |
US7569896(B2) |
申请公布日期 |
2009.08.04 |
申请号 |
US20060438711 |
申请日期 |
2006.05.22 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
KO CHIH-HSIN;KE CHUNG-HU;CHEN HUNG-WEI;LEE WEN-CHIN |
分类号 |
H01L29/78 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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