发明名称 STATE RETAINING POWER GATED LATCH AND METHOD THEREFOR
摘要 A circuit has first latch, a second latch, a coupling circuit, and a power down circuit. The first latch has an input/output coupled to a data node. The second latch has an input/output. The coupling circuit is coupled between the input/output of the second latch and the data node. The coupling circuit is enabled during a normal operation of the circuit and disabled during a power down mode of the circuit. The power down control circuit is for disabling the first latch during the power down mode and for a time period after a transition from the power down mode to the normal operation. This allows the second latch to set the state of the first latch when transitioning from the power down mode to the normal mode. Thus normal operation can be fast, and the power down mode can have low leakage current.
申请公布号 US2009189664(A1) 申请公布日期 2009.07.30
申请号 US20080022193 申请日期 2008.01.30
申请人 REMINGTON SCOTT I 发明人 REMINGTON SCOTT I.
分类号 H03K5/22 主分类号 H03K5/22
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