发明名称 PMOS TRANSISTOR STRAIN OPTIMIZATION WITH RAISED JUNCTION REGIONS
摘要 Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.
申请公布号 SG153631(A1) 申请公布日期 2009.07.29
申请号 SG20040029526 申请日期 2004.05.21
申请人 INTEL CORPORATION 发明人 BOHR MARK T.;GHANI TAHIR;CEA STEPHEN;MISTRY KAIZAD;AUTH CHRISTOPHER P.;ARMSTRONG MARK;ZAWADZKI KEITH E
分类号 H01L21/336;H01L21/8238;H01L29/78;(IPC1-7):H01L21/823 主分类号 H01L21/336
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