| 摘要 |
The invention relates to apparatus for controlling timeouts and delays of an error recovery procedure in a digital circuit, e.g. a microprocessor. The apparatus comprises a finite state machine (FSM) 10, having a plurality of states 12 and a plurality of transitions 14. Transitions 14 are arranged between two states 12 respectively. States 12 correspond with operation steps (40, 44, 52, 56, 58, 64) of the error recovery procedure, including error classification, a drain operation, a fence operation in which a microprocessor core does not communicate with memory, a reset or refresh operation, and automatic built-in self test (ABIST). Transitions 14 of the FSM 10 depend on conditions (46, 50, 53, 57, 59, 62) for the error recovery procedure. The FSM 10 is coupled with a timeout logic circuit 20 which controls a timer to obtain the timeouts (46, 53, 57, 59) of the error recovery procedure. The FSM is configurable by a data vector which describes states 12 of the FSM for which the timer should be engaged. |
